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Table 26. IEEE 1588 DC Electrical Characteristics
Characteristic
Input high voltage
Input low voltage
Input current
V IH
V IL
I IN
Symbol
Condition
—
—
0V ≤ V IN ≤ OV DD
Min
2.0
- 0.3
—
Max
OV DD + 0.3
0.8
±5
unit
V
V
μ A
8.3.4
IEEE 1588 AC Specifications
The IEEE 1588 AC timing specifications are given in the following table.
Table 27. IEEE 1588 AC Timing Specifications
At recommended operating conditions with OV DD of 3.3 V ± 300mV.
Parameter/Condition
QE_1588_CLK clock period
QE_1588_CLK duty cycle
QE_1588_CLK peak-to-peak jitter
Rise time QE_1588_CLK
Symbol
t T1588CLK
t T1588CLKH /t T1588CLK
t T1588CLKINJ
t T1588CLKINR
Min
2.5
40
—
1.0
Typ
—
50
—
—
Max
T RX_CLK × 9
60
250
2.0
Unit
ns
%
ps
ns
Note
1, 3
—
—
—
(20%–80%)
Fall time QE_1588_CLK
t T1588CLKINF
1.0
—
2.0
ns
—
(80%–20%)
QE_1588_CLK_OUT clock period
QE_1588_CLK_OUT duty cycle
t T1588CLKOUT
t T1588CLKOTH
2 × t T1588CLK
30
—
50
—
70
ns
%
—
—
/t T1588CLKOUT
QE _1588_PULSE_OUT
QE _1588_TRIG_IN pulse width
t T1588OV
t T1588TRIGH
0.5
2 × t T1588CLK_MAX
—
—
3.0
—
ns
ns
—
2
Notes:
1.T RX_CLK is the max clock period of QUICC engine receiving clock selected by TMR_CTRL[CKSEL]. See the MPC8309
PowerQUICC II Pro Integrated Communications Processor Reference Manual, for a description of TMR_CTRL registers.
2. It needs to be at least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC8309 PowerQUICC
II Pro Integrated Communications Processor Reference Manual, for a description of TMR_CTRL registers.
3. The maximum value of t T1588CLK is not only defined by the value of T RX_CLK , but also defined by the recovered clock. For
example, for 10/100 Mbps modes, the maximum value of t T1588CLK is 3600 and 280ns, respectively.
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
Freescale Semiconductor
29
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